Data processing systems utilize arithmetic calculation units for performing fixed or floating point calculations. One such system, for example, is utilized in a 32-bit processing system made and sold by Data General Corporation of Westboro, Massachusetts under the designation ECLIPSE.RTM. MV/8000. Such system utilizes an arithmetic logic unit which can perform both fixed point calculations and floating point calculations.
In performing floating point calculations, the arithmetic logic unit of such system can be operated to produce either "single precision" accuracy wherein the floating point mantissa result comprises 24 bits (the remaining 8 bits being designated as "guard bits" for use in rounding operations) or "double precision" accuracy in which the calculation is effectively a 64-bit operation wherein the floating point mantissa result comprises 56 bits (the remaining 8 bits being used for rounding in the same manner as in single precision operations). In the present ECLIPSE.RTM. MV/8000 system double precision operations are performed by the arithmetic logic unit as two sequential 32-bit operations so that the overall time required for double precision is substantially greater than that required for single precision operation.
It is desirable to be able to perform the double precision operation in substantially less time compared to that presently required for the double precision operations in the current system without greatly increasing the overall complexity or cost of the system in this regard.
An appropriate technique for doing so which has been suggested by the art involves the performance of floating point operations by a floating point arithmetic computation unit which is separate from the arithmetic computation unit which performs fixed point operations. The floating point unit would be capable of performing its operation on 32-bit or 64-bit words to achieve both single and double precision operations. Thus, such a system would utilize both an arithmetic logic unit (ALU) and a floating point unit (FPU), each having its own control store for storing its own microinstructions (i.e., microcode) which are used in performing the separate types of arithmetic calculations involved. Accordingly, the ALU control store would provide microcode for performing 32-bit fixed point operations while the FPU control store would provide microcode for performing both 32-bit and 64-bit floating point operations. The time required to perform a complete double precision floating point operation would be reduced over that required to perform such double precision floating point operations using only a single arithmetic logic unit which can operate only on 32-bit words at a time. Such an approach, however, requires the provision of an additional different control store with entirely different microcode for controlling the operation of the FPU independently and separately from the control store and microcode operation of the ALU.
Alternatively, it has been suggested that a single control store be used, which store, however, is considerably enlarged in comparison with that previously required when using a single arithmetic logic unit so as to provide completely different and separate sets of control fields for controlling the operation of the ALU and for controlling the operation of the FPU. The use of such an enlarged control store is required in order to accommodate a sufficient number of control fields to assure that such units are independently and effectively separately controlled.
It would be desirable, however, to be able to provide the above desired operation without the need for two separate control stores or for such an enlarged control store.